ENGR 851 - Advanced Microprocessor Architectures - Spring 2012
Instructor: Seapahn Megerian, Ph.D.
San Francisco State University
School of Engineering
ENGR 851 course bulletin
Contact Info and Office Hours:
|Email:||engr851 at seapahn.us|
|Office hours:||Thursdays after lecture and by appointment.|
Time and Place
Lecture, Thursday, 18:10-20:55, HSS 305
Engr 851 provides an overview of advanced topics in microprocessor design and computer architectures. In addition to delving into a wide array of traditional processor design issues such as computation models, instruction sets, memory organization, pipelining, speculative and out of order execution, superscalar, VLIW, and EPIC, class discussions will often revolve around current challenges, trends, and hot topics from both industrial and academic domains. The goal of the course is to present in-depth discussions in historic and state of the art architectures, while at the same time encouraging the exploration of options in the coming generations of post-"Moore's Law" age of computer design. Highly parallelized and massively multi-core (with hundreds, thousands, and even larger number of cores), the evolution of large-scale flash memories, and the ever increasing density of complex systems-on-chip are some of the factors that demand fundamental changes in how computer architects have been approaching new design problems. Students are expected to have taken an undergraduate level computer architecture course. Prior knowledge of operating systems, parallel programming, and multi-threading will be very helpful but is not required.
- Engr 456 - Computer Systems
- Engr 356 - Basic Computer Architecture
- Operating systems knowledge recommended.
- Background and relevant material will be reviewed as deemed necessary by the instructor.
10% - Class participation
40% - Midterm
50% - Final exam
Tentative Course Schedule:
- 1-26: Introductions, course overview, system-level performance metrics
- 2-02: Linux fundamentals needed for this course; SimpleScalar
- 2-09: RISC, CISC, EPIC, SuperScalar and VLIW. Multitasking vs Multithreading.
- 2-16: Pipelining and hazards
- 2-23: Register renaming, branch prediction, and speculative execution.
- 3-01: Pipelining, VLIW, and Superscalar continued
- 3-08: No Class: CS + Engineering Career Symposium - Looks like the event was (cancelled.)
- 3-15: Midterm review, sample problems
- 3-22: No Class: Spring Recess
- 3-29: Midterm - Take-home
- 4-05: Memory hierarchy, caching, and analysis
- 4-12: Memory continued, cache coherence
- 4-19: Virtual Memory
- 4-26: Virtual Memory continued, large scale data centers
- 5-03: Midterm results and review
- 5-10: Final exam review
The sections below will be regularly updated throughout the course so check back often!
- Background topics - Things that you should already be familiar with.
- Instructions for installing SimpleScalar and GCC cross-compiler
- From the instructions, you'll need:
- Worked fine for 10.04 ubuntu 32-bit.
- For 10.04 ubuntu 64-bit:
- export $HOST=i686-unknown-linux
- sudo apt-get install libc6-devi386
- Hint: In the instructions above, if you copy-paste the commands directly, they may not work. Note that "–host=$HOST" for example should be using the minus sign (-). The text in the instructions is using a special character that does not seem to be '-' (looks like it though).
- Alternate instructions for installing SimpleScalar and the cross compiler.
- My commands history for installing SimpleScalar on 32-bit Ubuntu 11.10.
- Simple multithreading in widnows. Updated: 2/11 - now with timing information and an example of mutex usage.
- Announcement from the department: Computer Science & Engineering Symposium. Thursday March 8th 5pm to 8pm, in Jack Adams Hall. No class meeting.
- Lecture Notes: 2-09 RISC, EPIC, Multithreading, ... (thanks Angela!)
- Reading assignments: Chapter 1 (Fundamentals) and Chapter 3 (Instruction Level Parallelism)
- Email Clarification: I have not actually sent an email about the career symposium. I only listed it here in the annoucements. Sorry for the confusion! The main email I have sent to the class is titled "Spring 2012 - Engr 851" sent on Feb 1st. If you have not received this (or enrolled after 2/1), please let me know your email.
- Homework 1 (no need to turn in).
- Reading assignments: Appendix A (instruction sets) and C (pipelining) in the book.
- Lecture Notes: 2-16 Superscalar and pipelining (thanks Vishakha!)
- Lecture Notes: 2-23 Register renaming, scheduling, and ILP (thanks Puneet!)
- Lecture Notes #1: 3-01 Branch prediction and speculative execution (thanks Saran!)
- Looking at the events calendar seems like this event was cancelled: Computer Science & Engineering Symposium. Thursday March 8th 5pm to 8pm, in Jack Adams Hall. Still no class meeting.
- See Midterm topics and some sample Midterm questions.
- Lecture Notes #2: 3-01 Branch prediction and speculative execution (thanks Poojal!)
- Midterm Exam: Due by 11:59pm Tuesday April 3, 2012
- Cache index/tag example from class here.
- 4-05 Memory and Caches (thanks Kailash!)
- Reading / Video Assignments:
- 4-12 Memory and Caches (thanks Yizhe!)
- 4-19 Virtual Memory (thanks Smitha!)
- sim-cache example command line:
sim-cache -cache:dl1 dl1:256:32:2:l -cache:il1 dl1 -cache:il2 none -cache:dl2 none program_name
- L1 unified cache, 256 lines (sets), block size 32 (bytes), 2-way set associative, LRU replacement
- L1 instruction cache (il1) points to data cache (dl1)
- No L2 caches
- 04-26 Context Switch (thanks Tri!)