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ENGR 851 - Advanced Microprocessor Architectures - Fall 2010

Instructor: Seapahn Megerian, Ph.D.
San Francisco State University
School of Engineering

ENGR 851 course bulletin

Contact Info and Office Hours:

Email:engr851 at
Office:SCI 170A
Office hours:Mondays after lecture and by appointment.

Time and Place

Lecture, Monday, 18:10-20:55, HSS 305


Course Description:

Engr 851 provides an overview of advanced topics in microprocessor design and computer architectures. In addition to delving into a wide array of traditional processor design issues such as computation models, instruction sets, memory organization, pipelining, speculative and out of order execution, superscalar, VLIW, and EPIC, class discussions will often revolve around current challenges, trends, and hot topics from both industrial and academic domains. The goal of the course is to present in-depth discussions in historic and state of the art architectures, while at the same time encouraging the exploration of options in the coming generations of post-"Moore's Law" age of computer design. Highly parallelized and massively multi-core (with hundreds, thousands, and even larger number of cores), the evolution of large-scale flash memories, and the ever increasing density of complex systems-on-chip are some of the factors that demand fundamental changes in how computer architects have been approaching new design problems. Students are expected to have taken an undergraduate level computer architecture course. Prior knowledge of operating systems, parallel programming, and multi-threading will be very helpful but is not required.


  • Engr 456 - Computer Systems
  • Engr 356 - Basic Computer Architecture
  • Operating systems knowledge recommended.
  • Background and relevant material will be reviewed as deemed necessary by the instructor.


10% - Class participation
40% - Midterm
50% - Final exam

Tentative Course Schedule:

  1. 8-30: Introductions and course overview
  2. 9-06: Labor Day: No Class
  3. 9-13: Background review; performance metrics
  4. 9-20: RISC, CISC, Stack Processors, etc; Performance and reliability calculations
  5. 9-27: Multithreading and parallel programming; Parallel algorithms
  6. 10-04: Pipelining and hazards
  7. 10-11: ILP, VLIW, Superscalar, and register renaming
  8. 10-18: Superscalar continued - scheduling
  9. 10-25: Midterm review
  10. 11-01: Midterm (no class)
  11. 11-08: Memory hierarchy, caching, and analysis
  12. 11-15: Memory continued, cache coherence
  13. 11-22: Recess: No Class.
  14. 11-29: Virtual Memory
  15. 12-06: Virtual Memory continued, Midterm review
  16. 12-13: Final exam review and announcements

The sections below will be regularly updated throughout the course so check back often!